Last updated March 16, 2014
The following are more details about the objectives.
The lab is Writing
Intensive. Therefore, lab reports will
be graded for writing style, which will count towards around 50% of the
overall grade. Good communication skills are important for any
successful engineer.
Written lab reports and demonstrations are graded as follows:
# |
Lab Asssignment |
#Weeks
[Points] |
Report
Grading Style |
Report
Due Dates |
0
|
Introduction
|
1 Week [0 pts] |
|
|
1
|
Measurement of TTL characteristics
|
1 Week [10 pts] |
Grading with revision |
First due date: TBA Revision due date: TBA |
2.1 |
Micro-Controllers:
Introduction to the PIC 16F84A
More Information |
1 Week [10 pts] |
Loose grading |
Due date: TBA |
2.2 |
Read before lab (30 minutes of reading):
Part 2
of overview of PIC
Read before lab (15 minutes of reading): Micro-Controllers: Traffic Light Controller Download testlab2.c |
1 Week [10 pts] |
Regular grading |
Due date: TBA |
2.3 |
Read
before lab (30 minutes of reading): Part 3
of overview of PIC Read before lab (30 minutes of reading): Micro-Controllers: Interrupts and Simulation in MPLAB |
1 Week [10 pts] |
Grading with revision |
First due date: TBA Revision due date: TBA |
3 |
CPU
Research
|
4 Weeks [30 pts] |
Grading with revision |
First due date: Nov. 1 Revision due date: TBA after you receive comments from your first submission |
4.1 |
Verilog
HDL and FGPAs: Part I -- under construction (It will cover introduction to FPGAs, FPGA design tools such as Xilinx Webpack, Digilent Basys boards, proper Verilog HDL design and functional simulation and testing.) Reading Assignment: Ciletti, For the first lab session read Chap 1 and 8. Optional reading is Chap 2. For the second lab session read Chapter 4. |
1 Week [10 pts] |
Loose grading |
Due date: TBA |
4.2 |
Verilog
HDL and FGPAs: Part
II -- under construction (It will cover synthesis and post synthesis design tasks.) Reading Assignment: Ciletti. For the first lab session read parts of Chap 6, and for the second lab session read parts of Chap 11. |
1 Week [10 pts] |
Loose grading |
Due date: TBA |
5 |
Final
Project: Pipeline CPU
Design and Implementation -- Under Construction |
4 Weeks [40 pts] |
Regular grading |
Due date: TBA |