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Date:  Thu, June 21, 2018
Time:  6:15pm
Location:  Holmes 244
Speaker:  Alvin Loke, Senior Director of Technology at Qualcomm

Sponsored by University of Hawaii IEEE Student Branch and IEEE Hawaii EDS/SSCS Joint Chapter

Abstract:

The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology elements enabling 7nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.

Biography:

Alvin Loke is a Senior Director of Technology at Qualcomm working on next-generation CMOS analog/mixed-signal design/technology co-optimization and wireline for mobile ICs. Prior to Qualcomm, he worked on CMOS process integration at HP Labs and Chartered Semiconductor before shifting to wireline design at Agilent and Advanced Micro Devices. He is an active volunteer at the IEEE Solid-State Circuits Society (SSCS), having served as a CICC committee member for 7 years, Chapter officer for 10 years, JSSC Guest Editor, and Distinguished Lecturer. He recently joined the VLSI Symposia committee and is the SSCS Webinar Coordinator for North America. For his service, he received the IEEE Region 5 Outstanding Member Service Award in 2010 and the Denver Chapter he chaired received the SSCS Outstanding Chapter Award in 2005. Alvin has authored several dozen publications (including a CICC 2018 Best Paper) and 25 patents. He received a B.A.Sc. in engineering physics with highest honors from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford.