What will be the next Big Thing? PC/Tablet peaked at 500M units/year in 2014 and Smartphone peaked at 1.5B units/year in 2019.  In celebration of the 75th anniversary of the transistor invention, this DL seminar talk will combine my IWJT June 2023 invited presentation on "CMOS Evolution 1980 to 2023" with my invited Dec/Jan2024 Electron Device Magazine article on "A Historical Review of Selective Epitaxial Growth: From 1962 to Present".

The 1980s: The US and Japan dominated the semiconductor industry. Traditional CMOS transistor design scaling and the industry transitioned from 3" wafers to 100mm (1979) to 125mm (1981) to 150mm (1984) and to 200mm (1987) putting economic stress on wafer and equipment manufacturers and lowered chip costs in agreement with Moore's Law (Gordon Moore from Intel). In the US, Bulk-CMOS transitioned to Epi-CMOS with single-well, twin-well and triple-well for Latch-up and soft-error rate immunity.  DRAM evolved from planar cell design to 3-D stacked capacitor (Japan & Micron) or trench capacitor (IBM, TI, Toshiba & Siemens) cell design and Flash memory was invented by Toshiba.    

The 1990s: 200mm wafer manufacturing required lower thermal budget processing to prevent wafer warpage using high energy ion implantation and RTA (rapid thermal annealing). Korea led by Samsung, Hyundai and LG took over the DRAM memory market.  Intel paved the way for 300mm wafers by 1999 and developed "copy exact" equipment for manufacturing.  At 0.18um node, they introduced notched poly-gate in 1999 and this required the switch from batch to single wafer implantation due to yield loss.  IBM introduced PD (partially depleted) SOI-CMOS at the 0.18um node in 1999.

The 2000s:   Intel also introduced the concept of "Equivalent Device Scaling" by using non-traditional transistor scaling methods to continue Moore's Law as their process technology know-how was one generation ahead of everyone else.  Reducing transistor leakage was key (gate leakage, gate edge leakage and S/D leakage).  In 2003 at 90nm node Intel introduced localized strain-Si technology using selective epi S/D technology for pMOS to boost transistor performance.  In 2007 at the 45nm node they were 1st to introduce High-k Metal Gate to reduce gate leakage, and in 2009 at the 32nm node they used Stacking Fault Stressor to boost nMOS performance.  The 450mm wafer and equipment push failed due to the high costs but the equipment designs were used for Flat Panel and Solar cell manufacturing requiring 3000+ wafers per hour throughputs.

The 2010s: In 2011 at the 22nm node Intel introduced 3-D FinFET CMOS transistor architecture.  DRAM evolved to recess channel design and Flash memory went to 3-D with multiple stacked layers from 24-layers in 2015 to >200-layers in the 2020s.

The 2020s: In 2022 at the 3nm node Samsung introduced the 3-D Gate-All-Around (Nano-Sheet) CMOS transistor.  It will evolve to Fork-sheet by 1.5nm (2028) and then stacked CMOS at 0.7nm (2034).  This requires new material modification and 2-D channel materials.

John Ogawa Borland graduated from Radford High School in Honolulu, HI.  He received his BS and MS degrees in Materials Science & Engineering from MIT.  His BS thesis research was InP Liquid Phase Epitaxial growth satellite solar cells at Hughes Malibu Research Lab, and his MS thesis research was InGaAsP Molecular Beam Epitaxial growth for communication devices at Nippon Telephone & Telegraph, Musashino Research Lab, Tokyo, Japan.  He published over 170 papers and was awarded 6 US patents and 2 Japanese patents. His career in the semiconductor industry covers 18 CMOS technology nodes from 1.25um to 3nm.  He is IEEE Region 6 Central Area chair, past Hawaii section chair, Hawaii EDS/SSCS chapter chair, Hawaii PES chapter chair and PES Humanitarian Activities Committee Global Ambassador.  A member of the Electrical Chemical Society and Material Research Society.