Challenges in the Design and Verification of Large Digital Circuits
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Date: Thu, April 25, 2013
Time: 10:00AM -- 11:00AM
Location: Holmes Hall 389
Speaker: Professor Peter-Michael Seidel Department of Information and Computer Sciences
Abstract: According to the international technology roadmap for semiconductors (ITRS) "verification has become the dominant cost in the modern hardware and software system design process," thereby restricting design sizes, and limiting design exploration and optimization that can be carried out in the tight schedules of general-purpose and application-specific processor developments. Rather than just blaming the scalability of verification approaches and tools for large circuits, I will address larger portions of the whole digital design cycle that have a direct impact on the verification complexity, the design overhead and the scalability of a digital design project, and I will point out opportunities to address the related challenges. During the discussion I will bring up observations from my previous work at AMD and point to previous research results, and I will discuss challenges for future investigation.
Bio: Dr. Peter-Michael Seidel has joined a faculty of the Information and Computer Science Department in Fall 2012. In Fall 2013 he will be teaching ICS331 Digital Logic Design and Microprocessors and ICS691 Formal Methods. Dr. Seidel's research interests are focusing on the effective use of formal methods for Computer Architecture, Software Design and Security Protocols. Other research interests include the areas of Computer Arithmetic, Computer Architecture and Application-Specific Processor Optimization. Prior to being at UH, Dr. Seidel he has been leading the formal verification of functional modules for two low-power commercial x86 CPU design projects at Advanced Micro Devices. Dr. Seidel is program chair of the IEEE International Symposium on Computer Arithmetic (ARITH) and a member of the steering committee for the IEEE International Conference on Computer Design (ICCD). He is a member of the ACM and a senior member of the IEEE.
Date: Thu, April 25, 2013
Time: 10:00AM -- 11:00AM
Location: Holmes Hall 389
Speaker: Professor Peter-Michael Seidel Department of Information and Computer Sciences
Abstract: According to the international technology roadmap for semiconductors (ITRS) "verification has become the dominant cost in the modern hardware and software system design process," thereby restricting design sizes, and limiting design exploration and optimization that can be carried out in the tight schedules of general-purpose and application-specific processor developments. Rather than just blaming the scalability of verification approaches and tools for large circuits, I will address larger portions of the whole digital design cycle that have a direct impact on the verification complexity, the design overhead and the scalability of a digital design project, and I will point out opportunities to address the related challenges. During the discussion I will bring up observations from my previous work at AMD and point to previous research results, and I will discuss challenges for future investigation.
Bio: Dr. Peter-Michael Seidel has joined a faculty of the Information and Computer Science Department in Fall 2012. In Fall 2013 he will be teaching ICS331 Digital Logic Design and Microprocessors and ICS691 Formal Methods. Dr. Seidel's research interests are focusing on the effective use of formal methods for Computer Architecture, Software Design and Security Protocols. Other research interests include the areas of Computer Arithmetic, Computer Architecture and Application-Specific Processor Optimization. Prior to being at UH, Dr. Seidel he has been leading the formal verification of functional modules for two low-power commercial x86 CPU design projects at Advanced Micro Devices. Dr. Seidel is program chair of the IEEE International Symposium on Computer Arithmetic (ARITH) and a member of the steering committee for the IEEE International Conference on Computer Design (ICCD). He is a member of the ACM and a senior member of the IEEE.