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Date:  Wed, March 11, 2015
Time:  6:30PM
Location:  Holmes Hall 244
Speaker:  John O. Borland, Senior Member IEEE, IEEE Hawaii Section Chair, J.O.B. Technologies

 Today the semiconductor industry is driven by smartphones and the multitude of devices such as state of the art 3-D FinFET 14nm technology node application processors (logic devices), 128Gb Flash memory devices at 16nm technology node, 3-D stacked backside CMOS image sensors with up to 20M pixels for cell phone cameras, and embedded DRAM. Continued reduction in form factor and device packing density is achieved with More Moore 3-D device scaling and More than Moore 3-D stacked devices. This presentation will 1st discuss the DRAM device scaling from 3-D trench or stack capacitor cell starting at 4Mb DRAM in 1986 at the 0.7um technology node to 3-D device channels in the 2000’s and then the 3-D vertical gate design. Backside CMOS image sensors with 3-D stacked die/chip was 1st introduced into production by Sony in 2012 and is now used in the Apple iPhone 5 & 6. In 2013 Samsung introduced into production the 1st 128Gb 3-D Flash memory chip using 32-layers of stacked polysilicon layers using 32nm technology with the equivalent die area as their 2-D planar 128Gb Flash memory using 16nm technology. For logic devices, Intel was 1st to switch from 2-D planar to 3-D FinFET in 2012 at 22nm technology node and the rest of the industry is making the switch now in 2015 using 14/16nm technology. Apple A9 processor will use 14/16nm 3-D FinFET technology for next generation iPhone 6 or 7 and Samsung Galaxy S6 with use Exynos 14nm 3-D FinFET technology for next generation Galaxy S6 starting this year in 2015. Samsung also announced in Feb 2015 3-D embedded package on package (ePoP) which stacks application processor + DRAM + Flash + Multimedia card saving 40% area. Finally 10nm (2016) and 7nm (2018) technology node using high mobility channel material and nano-wire device architectures will be discussed.

Bio:

John Ogawa Borland was raised in Hawaii attending Waipahu and Pearl Harbor Kai Elementary schools, Aliumanu Intermediate school and Radford High school. Senior year was an NSF-SSTP student at Chaminade College and also an Eagle Scout. He received his B.S. and M.S. degrees in Material Science and Engineering from the Massachusetts Institute of Technology (MIT) in Cambridge, MA. He completed his BS thesis research on InP Liquid Phase Epitaxial (LPE) crystal growth at Hughes Malibu Research Labs in 1980 and his MS thesis research on InP Molecular Beam Epitaxial (MBE) crystal growth at Nippon Telephone and Telegraph (NTT) Labs in Musashino, Tokyo, Japan in 1981. He is a senior member of IEEE and the IEEE Hawaii section chair for 2014 & 2015. He is also a member of the Electrochemical Society (ECS) and was co-organizer for various ECS technical conferences/symposium including the Symposium on ULSI Process Integration (2001, 2003 & 2005), Semiconductor Silicon (1994 & 1998) and Chemical Vapor Deposition (1987, 1989, & 1991). He also is advisory committee co-chair for the IEEE International Workshop on Junction Technology (2008, 2010, 2011, 2012, 2013 and 2014) held in Kyoto, Japan and Shanghai, China. He has published over 134 technical and invited papers around the world in the areas of advanced semiconductor device manufacturing techniques and high efficiency c-Si solar cells and has been awarded 6 patents.

He was Director of Operations of APIC’s subsidiary Advanced Integrated Photonics which is their Silicon Photonics Foundry Fab in Honolulu, Hawaii from April 2013 to August 2014. In June 2003 he founded JOB Technologies a strategic marketing, sales and technology consulting company providing service to the semiconductor device manufacturing and equipment companies focusing in the area of 10nm and 7nm node front end of line process development. Through his consulting activities he was involved in: 1) strategic marketing and sales of front end of line equipment, 2) high-k gate dielectric process development, 3) developing new metrologies to accurately characterize ultra-shallow junctions, 4) new diffusion-less processing techniques to achieve USJ with semiconductor IC and equipment companies and 5) creating a new market for and invented/patented localized and blanket Ge processing for high mobility channel material and continued device scaling . From July 1998 to May 2003 he was Director of Advanced Business Development at Varian Semiconductor Equipment Associates. While at VSEA, he invented/patented the high tilt high current PoGI (Post Gate Implant) process for process simplification and improved device lateral channel and source drain engineering. He also led the revived interest in low temperature diffusion-less activation by solid phase epitaxy (SPE) for USJ (ultra-shallow junction) and its inclusion in the 2003 ITRS roadmap. From Nov. 1992 to July 1998 he was Vice President of Strategic Technology at Genus and invented/patented the MeV BILLI (Buried Implanted Layer for Lateral Isolation) structure for CMOS epi replacement, process simplification and improved latch-up performance. From Sept. 1983 to Nov. 1992 he was at Applied Materials and pioneering advanced silicon epitaxial and polysilicon/amorphous deposition techniques and equipment designs for blanket epi and polysilicon. He also patented some of his work on selective epi growth (SEG) and selective poly including surface interface cleaning techniques. This led to the successful implementation of SEG for local strap and elevated source drain by IBM in their 4Mb DRAM manufacturing in 1987. Also, a variation to his epitaxial lateral overgrowth (ELO) for SOI was used for epitaxial bonded SOI wafer manufacturing by ELTRAN (Cannon). From Aug. 1981 to Sept. 1983 he was at National Semiconductor Corp. developing the VHSIC-CMOS front end processing including bulk and epi wafer intrinsic gettering for improved gate oxide integrity and yield as well as substrate and CMOS well engineering for improved latch-up immunity.