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Beyond CMOS Technology and Evolutionary Architectures


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Date:  Thu, December 04, 2008
Time:  4:30 PM
Location:  Holmes Hall 389
Speaker:  Professor Pinaki Mazumder

Abstract:

Conventional shrinking methods to improve VLSI chip performance by continual scaling of device and interconnect geometries may allow CMOS juggernaut to reach about 25 nm nodes. During the post-shrinking era, a slew of mesoscopic and nanoscale technologies such as quantum tunneling devices, plasmon based transistors, ionic transport based crossbar structures, carbon nano-tube FET’s, grapheme FET’s, self-assembled array of quantum dots, and molecular devices are likely to emerge as commercially viable technologies in order to sustain the demands for exponential economic growth throughout the first quarter of the 21st Century.

Quantum tunneling in nanometric devices augurs a revolutionary shift of paradigm for circuit and CAD tools design that must account for quantum effects as well as local interactions between self-assembled circuit elements. These circuit elements may consist of a 2-dimensional array of self-organized quantum dots that can be instrumented to perform cellular automata class of algorithms or a 3-dimensional array of self-organized nanowires to perform a random Boolean network (RBN) class of algorithms. The talk will also briefly introduce neuromorphic nanoarchitectures consisting of 2-D array of amorphous-Silicon based memristor devices and also THz digital systems deploying surface plasmon polariton (SPP).

Biography: 

Pinaki Mazumder received his Ph.D. from the University of Illinois at Urbana-Champaign in 1988. He is a Professor of Electrical Engineering and Computer Science at the University of Michigan.Currently, he is on leave for two years from the UM to serve as the lead Program Director of the Emerging Models and Technologies Program at the US National Science Foundation. He had worked for six years in
industrial R&D centers that included AT&T Bell Laboratories, where in 1985 he started the CONES project - the first C modeling based VLSI synthesis tool, and India’s premiere electronics company, Bharat Electronics Ltd., where he had developed several high-speed and high-voltage analog integrated circuits intended for consumer electronics products. He has published over 230 technical papers and 4 books on various aspects of VLSI research works. His research interest includes current problems in Nanoscale CMOS VLSI design, CAD tools and circuit designs for emerging technologies including Quantum MOS and resonant tunneling devices, semiconductor memory systems, and physical synthesis of VLSI chips. Dr. Mazumder was a recipient of Digital's Incentives for Excellence Award, BF Goodrich National Collegiate Invention Award, and DARPA Research Excellence Award. Dr. Mazumder is an AAAS Fellow (2007) and an IEEE Fellow (1999) for his contributions to the field of VLSI.


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